The NB3H83905C is a 1.8 V, 2.5 V or 3.3 V VDD core Crystal input to 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by flexible 1.8 V, 2.5 V, or 3.3 V supply VDDO (with VDD ≥ VDDO). The device accepts a fundamental Parallel Resonant crystal from 3 MHz to 40 MHz or a single−ended LVCMOS Clock from up to 100 MHz.

Two synchronous LVTTL/LVCMOS Enable lines permit independent control over outputs BCLK[0:4] and output BCLK5; enabling or disabling only when the output is in LOW state eliminating potential output glitching or runt pulse generation. When unused, leave floating open, pins will default to HIGH state.

The 6 outputs drive 50 series or parallel terminated transmission lines. Parallel termination should be to 1/2 VCC. Series terminated lines can drive 2 loads each, or 12 lines total.

Fit, Form, and Function compatible with ICS83905 and PI6C10806.