The 74HCT109PW,118 is a dual positive-edge triggered JK flip-flop with set and reset from Nexperia. This device features separate clock, reset (CLR), and set (SET) inputs, and complementary Q and Q\ outputs. It is part of the 74HCT family, which offers TTL-compatible input thresholds while maintaining CMOS low power consumption. The positive-edge triggering ensures that the flip-flop changes state only on the rising edge of the clock signal. It is supplied in a TSSOP-16 package.

Applications

• Shift registers
• Counters
• Frequency dividers
• Control circuits
• Data storage

Features

• Dual JK flip-flop
• Positive-edge triggered clock input
• Separate set and reset inputs
• Complementary Q and Q\ outputs
• TTL-compatible input thresholds
• CMOS low power consumption
• TSSOP-16 package

Benefits

• Versatile functionality due to JK flip-flop operation with set and reset.
• Easy integration with TTL logic due to TTL-compatible inputs.
• Reduced power consumption compared to TTL logic.
• Simplified design due to positive-edge triggering.
• Space-saving due to the TSSOP-16 package.

The 74HCT109PW,118 provides a reliable and versatile solution for implementing sequential logic functions. Its TTL-compatible inputs and low power consumption make it suitable for a wide range of applications. The separate set and reset inputs allow for asynchronous control of the flip-flop state. The device is available in a TSSOP-16 package for easy surface mount assembly.

Technical Specifications:

• Supply Voltage: 4.5 V to 5.5 V
• Operating Temperature: -40°C to +125°C
• Input Type: TTL Compatible
• Package: TSSOP-16
• Maximum Clock Frequency: Typically 37 MHz
• Quiescent Current: Typically 8 μA